Fix the LLC regressions on X86 last night. In particular, when undoing

previous copy elisions and we discover we need to reload a register, make
sure to use the regclass of the original register for the reload, not the
class of the current register.  This avoid using 16-bit loads to reload 32-bit
values.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23645 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 12 insertions, 5 deletions

diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp
index f7306c5d0a..26498b7ec1 100644
--- a/lib/CodeGen/VirtRegMap.cpp
+++ b/lib/CodeGen/VirtRegMap.cpp
@@ -266,9 +266,14 @@ namespace {
 
     // AssignedPhysReg - The physreg that was assigned for use by the reload.
     unsigned AssignedPhysReg;
-
-    ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr)
-      : Operand(o), StackSlot(ss), PhysRegReused(prr), AssignedPhysReg(apr) {}
+    
+    // VirtReg - The virtual register itself.
+    unsigned VirtReg;
+
+    ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
+             unsigned vreg)
+      : Operand(o), StackSlot(ss), PhysRegReused(prr), AssignedPhysReg(apr),
+      VirtReg(vreg) {}
   };
 }
 
@@ -381,7 +386,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, const VirtRegMap &VRM) {
         // case, we actually insert a reload for V1 in R1, ensuring that
         // we can get at R0 or its alias.
         ReusedOperands.push_back(ReusedOp(i, StackSlot, PhysReg,
-                                          VRM.getPhys(VirtReg)));
+                                          VRM.getPhys(VirtReg), VirtReg));
         ++NumReused;
         continue;
       }
@@ -409,8 +414,10 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, const VirtRegMap &VRM) {
               // Okay, we found out that an alias of a reused register
               // was used.  This isn't good because it means we have
               // to undo a previous reuse.
+              const TargetRegisterClass *AliasRC =
+                MBB.getParent()->getSSARegMap()->getRegClass(Op.VirtReg);
               MRI->loadRegFromStackSlot(MBB, &MI, Op.AssignedPhysReg,
-                                        Op.StackSlot, RC);
+                                        Op.StackSlot, AliasRC);
               ClobberPhysReg(Op.AssignedPhysReg, SpillSlotsAvailable,
                              PhysRegsAvailable);