Two-address instructions no longer have to be A := A op C. Now any pair of dest / src operands can be tied together.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31363 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 119 insertions, 100 deletions

diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp
index 7db9958bc0..50599c850d 100644
--- a/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -95,122 +95,141 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
          mi != me; ++mi) {
       unsigned opcode = mi->getOpcode();
 
-      // ignore if it is not a two-address instruction
-      if (!TII.isTwoAddrInstr(opcode))
-        continue;
-
-      ++NumTwoAddressInstrs;
-      DEBUG(std::cerr << '\t'; mi->print(std::cerr, &TM));
-      assert(mi->getOperand(1).isRegister() && mi->getOperand(1).getReg() &&
-             mi->getOperand(1).isUse() && "two address instruction invalid");
-
-      // if the two operands are the same we just remove the use
-      // and mark the def as def&use, otherwise we have to insert a copy.
-      if (mi->getOperand(0).getReg() != mi->getOperand(1).getReg()) {
-        // rewrite:
-        //     a = b op c
-        // to:
-        //     a = b
-        //     a = a op c
-        unsigned regA = mi->getOperand(0).getReg();
-        unsigned regB = mi->getOperand(1).getReg();
-
-        assert(MRegisterInfo::isVirtualRegister(regA) &&
-               MRegisterInfo::isVirtualRegister(regB) &&
-               "cannot update physical register live information");
+      bool FirstTied = true;
+      for (unsigned si = 1, e = TII.getNumOperands(opcode); si < e; ++si) {
+        int ti = TII.getOperandConstraint(opcode, si, TargetInstrInfo::TIED_TO);
+        if (ti == -1)
+          continue;
+
+        if (FirstTied) {
+          ++NumTwoAddressInstrs;
+          DEBUG(std::cerr << '\t'; mi->print(std::cerr, &TM));
+        }
+        FirstTied = false;
+
+        assert(mi->getOperand(si).isRegister() && mi->getOperand(si).getReg() &&
+               mi->getOperand(si).isUse() && "two address instruction invalid");
+
+        // if the two operands are the same we just remove the use
+        // and mark the def as def&use, otherwise we have to insert a copy.
+        if (mi->getOperand(ti).getReg() != mi->getOperand(si).getReg()) {
+          // rewrite:
+          //     a = b op c
+          // to:
+          //     a = b
+          //     a = a op c
+          unsigned regA = mi->getOperand(ti).getReg();
+          unsigned regB = mi->getOperand(si).getReg();
+
+          assert(MRegisterInfo::isVirtualRegister(regA) &&
+                 MRegisterInfo::isVirtualRegister(regB) &&
+                 "cannot update physical register live information");
 
 #ifndef NDEBUG
-        // First, verify that we do not have a use of a in the instruction (a =
-        // b + a for example) because our transformation will not work. This
-        // should never occur because we are in SSA form.
-        for (unsigned i = 1; i != mi->getNumOperands(); ++i)
-          assert(!mi->getOperand(i).isRegister() ||
-                 mi->getOperand(i).getReg() != regA);
+          // First, verify that we don't have a use of a in the instruction (a =
+          // b + a for example) because our transformation will not work. This
+          // should never occur because we are in SSA form.
+          for (unsigned i = 0; i != mi->getNumOperands(); ++i)
+            assert((int)i == ti ||
+                   !mi->getOperand(i).isRegister() ||
+                   mi->getOperand(i).getReg() != regA);
 #endif
 
-        // If this instruction is not the killing user of B, see if we can
-        // rearrange the code to make it so.  Making it the killing user will
-        // allow us to coalesce A and B together, eliminating the copy we are
-        // about to insert.
-        if (!LV.KillsRegister(mi, regB)) {
-          const TargetInstrDescriptor &TID = TII.get(opcode);
-
-          // If this instruction is commutative, check to see if C dies.  If so,
-          // swap the B and C operands.  This makes the live ranges of A and C
-          // joinable.
-          if (TID.Flags & M_COMMUTABLE) {
-            assert(mi->getOperand(2).isRegister() &&
-                   "Not a proper commutative instruction!");
-            unsigned regC = mi->getOperand(2).getReg();
-            if (LV.KillsRegister(mi, regC)) {
-              DEBUG(std::cerr << "2addr: COMMUTING  : " << *mi);
-              MachineInstr *NewMI = TII.commuteInstruction(mi);
-              if (NewMI == 0) {
-                DEBUG(std::cerr << "2addr: COMMUTING FAILED!\n");
-              } else {
-                DEBUG(std::cerr << "2addr: COMMUTED TO: " << *NewMI);
-                // If the instruction changed to commute it, update livevar.
-                if (NewMI != mi) {
-                  LV.instructionChanged(mi, NewMI);  // Update live variables
-                  mbbi->insert(mi, NewMI);           // Insert the new inst
-                  mbbi->erase(mi);                   // Nuke the old inst.
-                  mi = NewMI;
+          // If this instruction is not the killing user of B, see if we can
+          // rearrange the code to make it so.  Making it the killing user will
+          // allow us to coalesce A and B together, eliminating the copy we are
+          // about to insert.
+          if (!LV.KillsRegister(mi, regB)) {
+            const TargetInstrDescriptor &TID = TII.get(opcode);
+
+            // If this instruction is commutative, check to see if C dies.  If
+            // so, swap the B and C operands.  This makes the live ranges of A
+            // and C joinable.
+            // FIXME: This code also works for A := B op C instructions.
+            if ((TID.Flags & M_COMMUTABLE) && mi->getNumOperands() == 3) {
+              assert(mi->getOperand(3-si).isRegister() &&
+                     "Not a proper commutative instruction!");
+              unsigned regC = mi->getOperand(3-si).getReg();
+              if (LV.KillsRegister(mi, regC)) {
+                DEBUG(std::cerr << "2addr: COMMUTING  : " << *mi);
+                MachineInstr *NewMI = TII.commuteInstruction(mi);
+                if (NewMI == 0) {
+                  DEBUG(std::cerr << "2addr: COMMUTING FAILED!\n");
+                } else {
+                  DEBUG(std::cerr << "2addr: COMMUTED TO: " << *NewMI);
+                  // If the instruction changed to commute it, update livevar.
+                  if (NewMI != mi) {
+                    LV.instructionChanged(mi, NewMI);  // Update live variables
+                    mbbi->insert(mi, NewMI);           // Insert the new inst
+                    mbbi->erase(mi);                   // Nuke the old inst.
+                    mi = NewMI;
+                  }
+
+                  ++NumCommuted;
+                  regB = regC;
+                  goto InstructionRearranged;
                 }
-
-                ++NumCommuted;
-                regB = regC;
-                goto InstructionRearranged;
               }
             }
+
+            // If this instruction is potentially convertible to a true
+            // three-address instruction,
+            if (TID.Flags & M_CONVERTIBLE_TO_3_ADDR)
+              // FIXME: This assumes there are no more operands which are tied
+              // to another register.
+#ifndef NDEBUG
+              for (unsigned i = si+1, e = TII.getNumOperands(opcode); i < e; ++i)
+                assert(TII.getOperandConstraint(opcode, i,
+                                                TargetInstrInfo::TIED_TO) == -1);
+#endif
+
+              if (MachineInstr *New = TII.convertToThreeAddress(mi)) {
+                DEBUG(std::cerr << "2addr: CONVERTING 2-ADDR: " << *mi);
+                DEBUG(std::cerr << "2addr:         TO 3-ADDR: " << *New);
+                LV.instructionChanged(mi, New);  // Update live variables
+                mbbi->insert(mi, New);           // Insert the new inst
+                mbbi->erase(mi);                 // Nuke the old inst.
+                mi = New;
+                ++NumConvertedTo3Addr;
+                assert(!TII.isTwoAddrInstr(New->getOpcode()) &&
+                       "convertToThreeAddress returned a 2-addr instruction??");
+                // Done with this instruction.
+                break;
+              }
           }
-          // If this instruction is potentially convertible to a true
-          // three-address instruction,
-          if (TID.Flags & M_CONVERTIBLE_TO_3_ADDR)
-            if (MachineInstr *New = TII.convertToThreeAddress(mi)) {
-              DEBUG(std::cerr << "2addr: CONVERTING 2-ADDR: " << *mi);
-              DEBUG(std::cerr << "2addr:         TO 3-ADDR: " << *New);
-              LV.instructionChanged(mi, New);  // Update live variables
-              mbbi->insert(mi, New);           // Insert the new inst
-              mbbi->erase(mi);                 // Nuke the old inst.
-              mi = New;
-              ++NumConvertedTo3Addr;
-              assert(!TII.isTwoAddrInstr(New->getOpcode()) &&
-                     "convertToThreeAddress returned a 2-addr instruction??");
-              // Done with this instruction.
-              continue;
-            }
-        }
-      InstructionRearranged:
-        const TargetRegisterClass* rc = MF.getSSARegMap()->getRegClass(regA);
-        MRI.copyRegToReg(*mbbi, mi, regA, regB, rc);
 
-        MachineBasicBlock::iterator prevMi = prior(mi);
-        DEBUG(std::cerr << "\t\tprepend:\t"; prevMi->print(std::cerr, &TM));
+        InstructionRearranged:
+          const TargetRegisterClass* rc = MF.getSSARegMap()->getRegClass(regA);
+          MRI.copyRegToReg(*mbbi, mi, regA, regB, rc);
+
+          MachineBasicBlock::iterator prevMi = prior(mi);
+          DEBUG(std::cerr << "\t\tprepend:\t"; prevMi->print(std::cerr, &TM));
 
-        // Update live variables for regA
-        LiveVariables::VarInfo& varInfo = LV.getVarInfo(regA);
-        varInfo.DefInst = prevMi;
+          // Update live variables for regA
+          LiveVariables::VarInfo& varInfo = LV.getVarInfo(regA);
+          varInfo.DefInst = prevMi;
 
-        // update live variables for regB
-        if (LV.removeVirtualRegisterKilled(regB, mbbi, mi))
-          LV.addVirtualRegisterKilled(regB, prevMi);
+          // update live variables for regB
+          if (LV.removeVirtualRegisterKilled(regB, mbbi, mi))
+            LV.addVirtualRegisterKilled(regB, prevMi);
 
-        if (LV.removeVirtualRegisterDead(regB, mbbi, mi))
-          LV.addVirtualRegisterDead(regB, prevMi);
+          if (LV.removeVirtualRegisterDead(regB, mbbi, mi))
+            LV.addVirtualRegisterDead(regB, prevMi);
 
-        // replace all occurences of regB with regA
-        for (unsigned i = 1, e = mi->getNumOperands(); i != e; ++i) {
-          if (mi->getOperand(i).isRegister() &&
-              mi->getOperand(i).getReg() == regB)
-            mi->getOperand(i).setReg(regA);
+          // replace all occurences of regB with regA
+          for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
+            if (mi->getOperand(i).isRegister() &&
+                mi->getOperand(i).getReg() == regB)
+              mi->getOperand(i).setReg(regA);
+          }
         }
-      }
 
-      assert(mi->getOperand(0).isDef() && mi->getOperand(1).isUse());
-      mi->getOperand(1).setReg(mi->getOperand(0).getReg());
-      MadeChange = true;
+        assert(mi->getOperand(ti).isDef() && mi->getOperand(si).isUse());
+        mi->getOperand(ti).setReg(mi->getOperand(si).getReg());
+        MadeChange = true;
 
-      DEBUG(std::cerr << "\t\trewrite to:\t"; mi->print(std::cerr, &TM));
+        DEBUG(std::cerr << "\t\trewrite to:\t"; mi->print(std::cerr, &TM));
+      }
     }
   }