diff options
author | Evan Cheng <evan.cheng@apple.com> | 2008-02-13 02:46:49 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2008-02-13 02:46:49 +0000 |
commit | a4d16a1f0dcdd1ab2862737105f900e2c577532d (patch) | |
tree | f38e5bb414e8aa878dd234e6fd09604248a33c0e /lib/CodeGen/TargetInstrInfoImpl.cpp | |
parent | 1eb5cf9c7d0b0b04402eddc007b0de414488baf4 (diff) |
commuteInstr() can now commute non-ssa machine instrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47043 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/TargetInstrInfoImpl.cpp')
-rw-r--r-- | lib/CodeGen/TargetInstrInfoImpl.cpp | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/lib/CodeGen/TargetInstrInfoImpl.cpp b/lib/CodeGen/TargetInstrInfoImpl.cpp index cd2bfcce02..598b94af9c 100644 --- a/lib/CodeGen/TargetInstrInfoImpl.cpp +++ b/lib/CodeGen/TargetInstrInfoImpl.cpp @@ -23,8 +23,17 @@ MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI) const { "This only knows how to commute register operands so far"); unsigned Reg1 = MI->getOperand(1).getReg(); unsigned Reg2 = MI->getOperand(2).getReg(); + MachineOperand &MO = MI->getOperand(0); + bool UpdateReg0 = MO.isReg() && MO.getReg() == Reg1; bool Reg1IsKill = MI->getOperand(1).isKill(); bool Reg2IsKill = MI->getOperand(2).isKill(); + if (UpdateReg0) { + // Must be two address instruction! + assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) && + "Expecting a two-address instruction!"); + Reg2IsKill = false; + MI->getOperand(0).setReg(Reg2); + } MI->getOperand(2).setReg(Reg1); MI->getOperand(1).setReg(Reg2); MI->getOperand(2).setIsKill(Reg1IsKill); |