diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2011-06-27 21:26:13 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2011-06-27 21:26:13 +0000 |
| commit | 15993f83a419950f06d2879d6701530ae6449317 (patch) | |
| tree | 749e4564ae6f9d1f7c3539ccec1dfd88e1642bc9 /lib/CodeGen/StackSlotColoring.cpp | |
| parent | bea6f615eefae279e53bbb63a31d2c3c67274c45 (diff) | |
More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133944 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/StackSlotColoring.cpp')
| -rw-r--r-- | lib/CodeGen/StackSlotColoring.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/CodeGen/StackSlotColoring.cpp b/lib/CodeGen/StackSlotColoring.cpp index 01f5b5627f..aefaa1098b 100644 --- a/lib/CodeGen/StackSlotColoring.cpp +++ b/lib/CodeGen/StackSlotColoring.cpp @@ -521,7 +521,7 @@ bool StackSlotColoring::PropagateBackward(MachineBasicBlock::iterator MII, if (MO.getSubReg() || MII->isSubregToReg()) return false; - const TargetRegisterClass *RC = TID.OpInfo[i].getRegClass(TRI); + const TargetRegisterClass *RC = TII->getRegClass(TID, i, TRI); if (RC && !RC->contains(NewReg)) return false; @@ -583,7 +583,7 @@ bool StackSlotColoring::PropagateForward(MachineBasicBlock::iterator MII, if (MO.getSubReg()) return false; - const TargetRegisterClass *RC = TID.OpInfo[i].getRegClass(TRI); + const TargetRegisterClass *RC = TII->getRegClass(TID, i, TRI); if (RC && !RC->contains(NewReg)) return false; if (MO.isKill()) |