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authorBruno Cardoso Lopes <bruno.cardoso@gmail.com>2011-02-07 19:38:32 +0000
committerBruno Cardoso Lopes <bruno.cardoso@gmail.com>2011-02-07 19:38:32 +0000
commite7a54520b3435c006c4f97c56fe970350981ea3c (patch)
treeea97da534cd194fac18585ee6b53e9200695e78b /lib/CodeGen/SimpleRegisterCoalescing.cpp
parenta5f2601e4d75e6c83d7b2c439f5a25001c342354 (diff)
Implement support for custom target specific asm parsing of operands.
Motivation: Improve the parsing of not usual (different from registers or immediates) operand forms. This commit implements only the generic support. The ARM specific modifications will come next. A table like the one below is autogenerated for every instruction containing a 'ParserMethod' in its AsmOperandClass static const OperandMatchEntry OperandMatchTable[20] = { /* Mnemonic, Operand List Mask, Operand Class, Features */ { "cdp", 29 /* 0, 2, 3, 4 */, MCK_Coproc, Feature_IsThumb|Feature_HasV6 }, { "cdp", 58 /* 1, 3, 4, 5 */, MCK_Coproc, Feature_IsARM }, A matcher function very similar (but lot more naive) to MatchInstructionImpl scans the table. After the mnemonic match, the features are checked and if the "to be parsed" operand index is present in the mask, there's a real match. Then, a switch like the one below dispatch the parsing to the custom method provided in 'ParseMethod': case MCK_Coproc: return TryParseCoprocessorOperandName(Operands); git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125030 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SimpleRegisterCoalescing.cpp')
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