This is possible:

vr1 = extract_subreg vr2, 3
...
vr3 = extract_subreg vr1, 2
The end result is vr3 is equal to vr2 with subidx 2.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47592 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 8 insertions, 2 deletions

diff --git a/lib/CodeGen/SimpleRegisterCoalescing.cpp b/lib/CodeGen/SimpleRegisterCoalescing.cpp
index ba026d7daf..c723c9eeae 100644
--- a/lib/CodeGen/SimpleRegisterCoalescing.cpp
+++ b/lib/CodeGen/SimpleRegisterCoalescing.cpp
@@ -457,8 +457,14 @@ SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg,
       O.setSubReg(0);
     } else {
       unsigned OldSubIdx = O.getSubReg();
-      assert((!SubIdx || !OldSubIdx) && "Conflicting sub-register index!");
-      if (SubIdx)
+      // Sub-register indexes goes from small to large. e.g.
+      // RAX: 0 -> AL, 1 -> AH, 2 -> AX, 3 -> EAX
+      // EAX: 0 -> AL, 1 -> AH, 2 -> AX
+      // So RAX's sub-register 2 is AX, RAX's sub-regsiter 3 is EAX, whose
+      // sub-register 2 is also AX.
+      if (SubIdx && OldSubIdx && SubIdx != OldSubIdx)
+        assert(OldSubIdx < SubIdx && "Conflicting sub-register index!");
+      else if (SubIdx)
         O.setSubReg(SubIdx);
       O.setReg(DstReg);
     }