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| author | Johnny Chen <johnny.chen@apple.com> | 2010-03-17 23:14:23 +0000 |
|---|---|---|
| committer | Johnny Chen <johnny.chen@apple.com> | 2010-03-17 23:14:23 +0000 |
| commit | b675e255d0def28e9718c62336be6fd6e7a22e54 (patch) | |
| tree | 275c1afb9a954d95bc7b72631ec268444c3fbd4f /lib/CodeGen/SimpleRegisterCoalescing.cpp | |
| parent | 77bdc48eb66396cbc4f81bfd1ac9de257b83cf41 (diff) | |
Fixed a bug in the IT mask printing where T means the cond bit in the mask
matches that of Firstcond[0] and E means otherwise. The Firstcond[0] is also
tagged in the Mask to facilitate Asm printing. The disassembler also depends
on this arrangement. This is similar to what's described in A2.5.2 ITSTATE.
Ran:
utils/lit/lit.py test/CodeGen/ARM test/CodeGen/Thumb test/CodeGen/Thumb2
successfully.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98775 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SimpleRegisterCoalescing.cpp')
0 files changed, 0 insertions, 0 deletions