Fix some sub-reg coalescing bugs where the coalescer wasn't updating the resulting interval's register class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76458 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 18 insertions, 12 deletions

diff --git a/lib/CodeGen/SimpleRegisterCoalescing.cpp b/lib/CodeGen/SimpleRegisterCoalescing.cpp
index 0ce603cc6a..daf7d4d582 100644
--- a/lib/CodeGen/SimpleRegisterCoalescing.cpp
+++ b/lib/CodeGen/SimpleRegisterCoalescing.cpp
@@ -614,15 +614,17 @@ bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
     return false;
   if (TID.getNumDefs() != 1)
     return false;
-  // Make sure the copy destination register class fits the instruction
-  // definition register class. The mismatch can happen as a result of earlier
-  // extract_subreg, insert_subreg, subreg_to_reg coalescing.
-  const TargetRegisterClass *RC = getInstrOperandRegClass(tri_, TID, 0);
-  if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
-    if (mri_->getRegClass(DstReg) != RC)
+  if (DefMI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF) {
+    // Make sure the copy destination register class fits the instruction
+    // definition register class. The mismatch can happen as a result of earlier
+    // extract_subreg, insert_subreg, subreg_to_reg coalescing.
+    const TargetRegisterClass *RC = getInstrOperandRegClass(tri_, TID, 0);
+    if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
+      if (mri_->getRegClass(DstReg) != RC)
+        return false;
+    } else if (!RC->contains(DstReg))
       return false;
-  } else if (!RC->contains(DstReg))
-    return false;
+  }
 
   unsigned DefIdx = li_->getDefIndex(CopyIdx);
   const LiveRange *DLR= li_->getInterval(DstReg).getLiveRangeContaining(DefIdx);
@@ -1378,13 +1380,17 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
         }
       }
       if (SubIdx) {
-        if (isInsSubReg || isSubRegToReg) {
-          if (!DstIsPhys && !SrcIsPhys) {
+        if (!DstIsPhys && !SrcIsPhys) {
+          if (isInsSubReg || isSubRegToReg) {
             NewRC = tri_->getMatchingSuperRegClass(DstRC, SrcRC, SubIdx);
-            if (!NewRC)
-              return false;
+          } else // extract_subreg {
+            NewRC = tri_->getMatchingSuperRegClass(SrcRC, DstRC, SubIdx);
           }
+        if (!NewRC) {
+          DOUT << "\t Conflicting sub-register indices.\n";
+          return false;  // Not coalescable
         }
+
         unsigned LargeReg = isExtSubReg ? SrcReg : DstReg;
         unsigned SmallReg = isExtSubReg ? DstReg : SrcReg;
         unsigned Limit= allocatableRCRegs_[mri_->getRegClass(SmallReg)].count();