diff options
author | Lang Hames <lhames@gmail.com> | 2009-10-03 04:31:31 +0000 |
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committer | Lang Hames <lhames@gmail.com> | 2009-10-03 04:31:31 +0000 |
commit | 6cc91e39c04c0c00756e7667f623f787c4851439 (patch) | |
tree | 5d92eb0738ad4f7309c74ad7ef32e2f0800efb16 /lib/CodeGen/SimpleRegisterCoalescing.cpp | |
parent | cc3b0650f1feec45d1a2890b20c05c4b325f1788 (diff) |
Oops. Renamed remaining MachineInstrIndex references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83255 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SimpleRegisterCoalescing.cpp')
-rw-r--r-- | lib/CodeGen/SimpleRegisterCoalescing.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/CodeGen/SimpleRegisterCoalescing.cpp b/lib/CodeGen/SimpleRegisterCoalescing.cpp index 2884a78be3..af3d60d3b9 100644 --- a/lib/CodeGen/SimpleRegisterCoalescing.cpp +++ b/lib/CodeGen/SimpleRegisterCoalescing.cpp @@ -399,7 +399,7 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA, bool BHasPHIKill = BValNo->hasPHIKill(); SmallVector<VNInfo*, 4> BDeadValNos; VNInfo::KillSet BKills; - std::map<LiveIndex, MachineInstrIndex> BExtend; + std::map<LiveIndex, LiveIndex> BExtend; // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g. // A = or A, B @@ -494,7 +494,7 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(LiveInterval &IntA, AI != AE; ++AI) { if (AI->valno != AValNo) continue; LiveIndex End = AI->end; - std::map<LiveIndex, MachineInstrIndex>::iterator + std::map<LiveIndex, LiveIndex>::iterator EI = BExtend.find(End); if (EI != BExtend.end()) End = EI->second; @@ -549,7 +549,7 @@ static bool isSameOrFallThroughBB(MachineBasicBlock *MBB, /// from a physical register live interval as well as from the live intervals /// of its sub-registers. static void removeRange(LiveInterval &li, - LiveIndex Start, MachineInstrIndex End, + LiveIndex Start, LiveIndex End, LiveIntervals *li_, const TargetRegisterInfo *tri_) { li.removeRange(Start, End, true); if (TargetRegisterInfo::isPhysicalRegister(li.reg)) { |