diff options
| author | Chris Lattner <sabre@nondot.org> | 2009-07-29 21:36:49 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2009-07-29 21:36:49 +0000 |
| commit | 2a3868849438a0a0ad4f9a50f2b94eb1639b554e (patch) | |
| tree | 207c400577ae0d0da9afc4e32ae7c7eaabd04318 /lib/CodeGen/SimpleRegisterCoalescing.cpp | |
| parent | 20a2a0aff3221e2c777558d714753bae0f296c8d (diff) | |
inline the global 'getInstrOperandRegClass' function into its callers
now that TargetOperandInfo does the heavy lifting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77508 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SimpleRegisterCoalescing.cpp')
| -rw-r--r-- | lib/CodeGen/SimpleRegisterCoalescing.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/CodeGen/SimpleRegisterCoalescing.cpp b/lib/CodeGen/SimpleRegisterCoalescing.cpp index 7aa9cf543f..2478612d00 100644 --- a/lib/CodeGen/SimpleRegisterCoalescing.cpp +++ b/lib/CodeGen/SimpleRegisterCoalescing.cpp @@ -619,7 +619,7 @@ bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt, // Make sure the copy destination register class fits the instruction // definition register class. The mismatch can happen as a result of earlier // extract_subreg, insert_subreg, subreg_to_reg coalescing. - const TargetRegisterClass *RC = getInstrOperandRegClass(tri_, TID, 0); + const TargetRegisterClass *RC = TID.OpInfo[0].getRegClass(tri_); if (TargetRegisterInfo::isVirtualRegister(DstReg)) { if (mri_->getRegClass(DstReg) != RC) return false; |