Pool-allocation for MachineInstrs, MachineBasicBlocks, and

MachineMemOperands. The pools are owned by MachineFunctions.

This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53212 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 6 insertions, 6 deletions

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index 10a5e8c9df..d33f3d2cb6 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -670,7 +670,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
 }
 
 void ScheduleDAG::AddMemOperand(MachineInstr *MI, const MachineMemOperand &MO) {
-  MI->addMemOperand(MO);
+  MI->addMemOperand(*MF, MO);
 }
 
 /// getSubRegisterRegClass - Returns the register class of specified register
@@ -726,7 +726,7 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node,
     unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getValue();
 
     // Create the extract_subreg machine instruction.
-    MachineInstr *MI = BuildMI(TII->get(TargetInstrInfo::EXTRACT_SUBREG));
+    MachineInstr *MI = BuildMI(*MF, TII->get(TargetInstrInfo::EXTRACT_SUBREG));
 
     // Figure out the register class to create for the destreg.
     unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
@@ -772,7 +772,7 @@ void ScheduleDAG::EmitSubregNode(SDNode *Node,
     }
     
     // Create the insert_subreg or subreg_to_reg machine instruction.
-    MachineInstr *MI = BuildMI(TII->get(Opc));
+    MachineInstr *MI = BuildMI(*MF, TII->get(Opc));
     MI->addOperand(MachineOperand::CreateReg(VRBase, true));
     
     // If creating a subreg_to_reg, then the first input operand
@@ -829,7 +829,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, bool IsClone,
 #endif
 
     // Create the new machine instruction.
-    MachineInstr *MI = BuildMI(II);
+    MachineInstr *MI = BuildMI(*MF, II);
     
     // Add result register values for things that are defined by this
     // instruction.
@@ -853,7 +853,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, bool IsClone,
       else {
         DOUT << "Sched: COMMUTED TO: " << *NewMI;
         if (MI != NewMI) {
-          delete MI;
+          MF->DeleteMachineInstr(MI);
           MI = NewMI;
         }
         ++NumCommutes;
@@ -928,7 +928,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, bool IsClone,
       --NumOps;  // Ignore the flag operand.
       
     // Create the inline asm machine instruction.
-    MachineInstr *MI = BuildMI(TII->get(TargetInstrInfo::INLINEASM));
+    MachineInstr *MI = BuildMI(*MF, TII->get(TargetInstrInfo::INLINEASM));
 
     // Add the asm string as an external symbol operand.
     const char *AsmStr =