Beef up the interface to inline asm constraint parsing, making it more general, useful, and easier to use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25866 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 10 insertions, 3 deletions

diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index edb98f3817..c861762d16 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -243,15 +243,22 @@ bool TargetLowering::isMaskedValueZeroForTargetNode(const SDOperand &Op,
 
 std::vector<unsigned> TargetLowering::
 getRegForInlineAsmConstraint(const std::string &Constraint) const {
+  // Not a physreg, must not be a register reference or something.
+  if (Constraint[0] != '{') return std::vector<unsigned>();
+  assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
+
+  // Remove the braces from around the name.
+  std::string RegName(Constraint.begin()+1, Constraint.end()-1);
+  
   // Scan to see if this constraint is a register name.
   const MRegisterInfo *RI = TM.getRegisterInfo();
   for (unsigned i = 1, e = RI->getNumRegs(); i != e; ++i) {
     if (const char *Name = RI->get(i).Name)
-      if (StringsEqualNoCase(Constraint, Name))
+      if (StringsEqualNoCase(RegName, Name))
         return std::vector<unsigned>(1, i);
   }
-
-  // Not a physreg, must not be a register reference or something.
+  
+  // Unknown physreg.
   return std::vector<unsigned>();
 }