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| author | Chris Lattner <sabre@nondot.org> | 2006-02-02 06:43:15 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-02-02 06:43:15 +0000 |
| commit | 9a06cce0f2088a298f357b933fb7d8e268f6ca52 (patch) | |
| tree | f8432ddc0d871f1d9d008e2e51a4f16ffd9f19f7 /lib/CodeGen/SelectionDAG/TargetLowering.cpp | |
| parent | 1bac9410193495d82f643e40b74f8c755664a534 (diff) | |
Implement MaskedValueIsZero for ANY_EXTEND nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25900 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/TargetLowering.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/TargetLowering.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index c861762d16..c79045b885 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -154,6 +154,11 @@ bool TargetLowering::MaskedValueIsZero(const SDOperand &Op, case ISD::ZERO_EXTEND: SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType()); return MaskedValueIsZero(Op.getOperand(0),Mask & (~0ULL >> (64-SrcBits))); + case ISD::ANY_EXTEND: + // If the mask only includes bits in the low part, recurse. + SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType()); + if (Mask >> SrcBits) return false; // Use of unknown top bits. + return MaskedValueIsZero(Op.getOperand(0), Mask); case ISD::AssertZext: SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT()); return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. |