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authorDuncan Sands <baldrick@free.fr>2009-01-31 15:50:11 +0000
committerDuncan Sands <baldrick@free.fr>2009-01-31 15:50:11 +0000
commit92abc62399881ba9c525be80362c134ad836e2d9 (patch)
tree596a2370bbd0b6c4279966b6885420abb878ae13 /lib/CodeGen/SelectionDAG/TargetLowering.cpp
parentd1b5e3fad94d4a5203c0a355aa7d37c01abaca8c (diff)
Fix PR3401: when using large integers, the type
returned by getShiftAmountTy may be too small to hold shift values (it is an i8 on x86-32). Before and during type legalization, use a large but legal type for shift amounts: getPointerTy; afterwards use getShiftAmountTy, fixing up any shift amounts with a big type during operation legalization. Thanks to Dan for writing the original patch (which I shamelessly pillaged). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63482 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/TargetLowering.cpp')
-rw-r--r--lib/CodeGen/SelectionDAG/TargetLowering.cpp8
1 files changed, 5 insertions, 3 deletions
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index ebc5067c70..7d524753cd 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1651,19 +1651,21 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
if (ConstantSDNode *AndRHS =
dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
+ MVT ShiftTy = DCI.isBeforeLegalize() ?
+ getPointerTy() : getShiftAmountTy();
if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
// Perform the xform if the AND RHS is a single bit.
if (isPowerOf2_64(AndRHS->getZExtValue())) {
return DAG.getNode(ISD::SRL, VT, N0,
- DAG.getConstant(Log2_64(AndRHS->getZExtValue()),
- getShiftAmountTy()));
+ DAG.getConstant(Log2_64(AndRHS->getZExtValue()),
+ ShiftTy));
}
} else if (Cond == ISD::SETEQ && C1 == AndRHS->getZExtValue()) {
// (X & 8) == 8 --> (X & 8) >> 3
// Perform the xform if C1 is a single bit.
if (C1.isPowerOf2()) {
return DAG.getNode(ISD::SRL, VT, N0,
- DAG.getConstant(C1.logBase2(), getShiftAmountTy()));
+ DAG.getConstant(C1.logBase2(), ShiftTy));
}
}
}