diff options
| author | Bill Wendling <isanbard@gmail.com> | 2009-01-30 23:03:19 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2009-01-30 23:03:19 +0000 |
| commit | 7581bfa2757a3149c6d17c0fe592e5c3808aa843 (patch) | |
| tree | aa4421e3289933230b386bf830923af82743f9bf /lib/CodeGen/SelectionDAG/TargetLowering.cpp | |
| parent | a03e74bf6795478fd0b8d8d09b86ab517cda84b5 (diff) | |
Get rid of the non-DebugLoc-ified getNOT() method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63442 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/TargetLowering.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/TargetLowering.cpp | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 1f9d9cf9a7..ebc5067c70 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -1841,7 +1841,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1, default: assert(0 && "Unknown integer setcc!"); case ISD::SETEQ: // X == Y -> ~(X^Y) Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); - N0 = DAG.getNOT(Temp, MVT::i1); + N0 = DAG.getNOT(DebugLoc::getUnknownLoc(), Temp, MVT::i1); if (!DCI.isCalledByLegalizer()) DCI.AddToWorklist(Temp.getNode()); break; @@ -1850,28 +1850,28 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1, break; case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y - Temp = DAG.getNOT(N0, MVT::i1); + Temp = DAG.getNOT(DebugLoc::getUnknownLoc(), N0, MVT::i1); N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); if (!DCI.isCalledByLegalizer()) DCI.AddToWorklist(Temp.getNode()); break; case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X - Temp = DAG.getNOT(N1, MVT::i1); + Temp = DAG.getNOT(DebugLoc::getUnknownLoc(), N1, MVT::i1); N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); if (!DCI.isCalledByLegalizer()) DCI.AddToWorklist(Temp.getNode()); break; case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y - Temp = DAG.getNOT(N0, MVT::i1); + Temp = DAG.getNOT(DebugLoc::getUnknownLoc(), N0, MVT::i1); N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); if (!DCI.isCalledByLegalizer()) DCI.AddToWorklist(Temp.getNode()); break; case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X - Temp = DAG.getNOT(N1, MVT::i1); + Temp = DAG.getNOT(DebugLoc::getUnknownLoc(), N1, MVT::i1); N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); break; } |