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| author | Evan Cheng <evan.cheng@apple.com> | 2006-10-09 20:57:25 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2006-10-09 20:57:25 +0000 |
| commit | 466685d41a9ea4905b9486fea38e83802e46f196 (patch) | |
| tree | 5cce15f398aa815a729d1e74d62617d58a267bb8 /lib/CodeGen/SelectionDAG/TargetLowering.cpp | |
| parent | 24446e253a17720f6462288255ab5ebd13b8491f (diff) | |
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30844 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/TargetLowering.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/TargetLowering.cpp | 21 |
1 files changed, 12 insertions, 9 deletions
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 1c00c9136c..73cefc4e38 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -552,9 +552,10 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask, KnownOne = 0; break; } - case ISD::LOADX: { + case ISD::LOAD: { if (ISD::isZEXTLoad(Op.Val)) { - MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(3))->getVT(); + LoadSDNode *LD = cast<LoadSDNode>(Op); + MVT::ValueType VT = LD->getLoadVT(); KnownZero |= ~MVT::getIntVTBitMask(VT) & DemandedMask; } break; @@ -892,9 +893,10 @@ void TargetLowering::ComputeMaskedBits(SDOperand Op, uint64_t Mask, KnownOne = 0; return; } - case ISD::LOADX: { + case ISD::LOAD: { if (ISD::isZEXTLoad(Op.Val)) { - MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(3))->getVT(); + LoadSDNode *LD = cast<LoadSDNode>(Op); + MVT::ValueType VT = LD->getLoadVT(); KnownZero |= ~MVT::getIntVTBitMask(VT) & Mask; } return; @@ -1197,15 +1199,16 @@ unsigned TargetLowering::ComputeNumSignBits(SDOperand Op, unsigned Depth) const{ } // Handle LOADX separately here. EXTLOAD case will fallthrough. - if (Op.getOpcode() == ISD::LOADX) { - unsigned LType = Op.getConstantOperandVal(4); - switch (LType) { + if (Op.getOpcode() == ISD::LOAD) { + LoadSDNode *LD = cast<LoadSDNode>(Op); + unsigned ExtType = LD->getExtensionType(); + switch (ExtType) { default: break; case ISD::SEXTLOAD: // '17' bits known - Tmp = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT()); + Tmp = MVT::getSizeInBits(LD->getLoadVT()); return VTBits-Tmp+1; case ISD::ZEXTLOAD: // '16' bits known - Tmp = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT()); + Tmp = MVT::getSizeInBits(LD->getLoadVT()); return VTBits-Tmp; } } |