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| author | Chris Lattner <sabre@nondot.org> | 2006-02-21 23:11:00 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-02-21 23:11:00 +0000 |
| commit | 4217ca8dc175f7268a4335c8406dedd901e8e631 (patch) | |
| tree | 5b005d58753216105bb61c8ea24dfd5e1f6b00ec /lib/CodeGen/SelectionDAG/TargetLowering.cpp | |
| parent | aba3b13fb3e00b16725860e46a484c88136569f6 (diff) | |
Updates to match change of getRegForInlineAsmConstraint prototype
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26305 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/TargetLowering.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/TargetLowering.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 533499cbc0..79211debc9 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -745,7 +745,8 @@ bool TargetLowering::isOperandValidForConstraint(SDOperand Op, std::vector<unsigned> TargetLowering:: -getRegForInlineAsmConstraint(const std::string &Constraint) const { +getRegForInlineAsmConstraint(const std::string &Constraint, + MVT::ValueType VT) const { // Not a physreg, must not be a register reference or something. if (Constraint[0] != '{') return std::vector<unsigned>(); assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); |