Skeleton of the list schedule.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25544 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 4 insertions, 0 deletions

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index aa410bd0a6..6cc4d436e9 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -69,6 +69,8 @@ namespace {
       clEnumValN(simpleNoItinScheduling, "simple-noitin",
                  "Simple two pass scheduling: Same as simple "
                  "except using generic latency"),
+      clEnumValN(listSchedulingBURR, "list-BURR",
+                 "Bottom up register reduction list scheduling"),
       clEnumValEnd));
 } // namespace
 
@@ -1775,6 +1777,8 @@ void SelectionDAGISel::ScheduleAndEmitDAG(SelectionDAG &DAG) {
   case simpleNoItinScheduling:
     SL = createSimpleDAGScheduler(ISHeuristic, DAG, BB);
     break;
+  case listSchedulingBURR:
+    SL = createBURRListDAGScheduler(DAG, BB);
   }
   BB = SL->Run();
 }