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authorChris Lattner <sabre@nondot.org>2005-09-28 22:28:18 +0000
committerChris Lattner <sabre@nondot.org>2005-09-28 22:28:18 +0000
commit01b3d73c20f5afb8265ae943a8ba23c2238c5eea (patch)
tree068bdd7a7effd620fa1b0b735ffb37c6c2fa7319 /lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
parenta5cac6f6eb939b033c020cc59499756d2b95b349 (diff)
Add FP versions of the binary operators, keeping the int and fp worlds seperate.
Though I have done extensive testing, it is possible that this will break things in configs I can't test. Please let me know if this causes a problem and I'll fix it ASAP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23504 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp')
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp47
1 files changed, 35 insertions, 12 deletions
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index ad7a8af4af..9eb0ed9a4a 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -353,14 +353,34 @@ public:
//
void visitBinary(User &I, unsigned Opcode, bool isShift = false);
- void visitAdd(User &I) { visitBinary(I, ISD::ADD); }
+ void visitAdd(User &I) {
+ visitBinary(I, I.getType()->isFloatingPoint() ? ISD::FADD : ISD::ADD);
+ }
void visitSub(User &I);
- void visitMul(User &I) { visitBinary(I, ISD::MUL); }
+ void visitMul(User &I) {
+ visitBinary(I, I.getType()->isFloatingPoint() ? ISD::FMUL : ISD::MUL);
+ }
void visitDiv(User &I) {
- visitBinary(I, I.getType()->isUnsigned() ? ISD::UDIV : ISD::SDIV);
+ unsigned Opc;
+ const Type *Ty = I.getType();
+ if (Ty->isFloatingPoint())
+ Opc = ISD::FDIV;
+ else if (Ty->isUnsigned())
+ Opc = ISD::UDIV;
+ else
+ Opc = ISD::SDIV;
+ visitBinary(I, Opc);
}
void visitRem(User &I) {
- visitBinary(I, I.getType()->isUnsigned() ? ISD::UREM : ISD::SREM);
+ unsigned Opc;
+ const Type *Ty = I.getType();
+ if (Ty->isFloatingPoint())
+ Opc = ISD::FREM;
+ else if (Ty->isUnsigned())
+ Opc = ISD::UREM;
+ else
+ Opc = ISD::SREM;
+ visitBinary(I, Opc);
}
void visitAnd(User &I) { visitBinary(I, ISD::AND); }
void visitOr (User &I) { visitBinary(I, ISD::OR); }
@@ -491,14 +511,17 @@ void SelectionDAGLowering::visitBr(BranchInst &I) {
void SelectionDAGLowering::visitSub(User &I) {
// -0.0 - X --> fneg
- if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
- if (CFP->isExactlyValue(-0.0)) {
- SDOperand Op2 = getValue(I.getOperand(1));
- setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
- return;
- }
-
- visitBinary(I, ISD::SUB);
+ if (I.getType()->isFloatingPoint()) {
+ if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0)))
+ if (CFP->isExactlyValue(-0.0)) {
+ SDOperand Op2 = getValue(I.getOperand(1));
+ setValue(&I, DAG.getNode(ISD::FNEG, Op2.getValueType(), Op2));
+ return;
+ }
+ visitBinary(I, ISD::FSUB);
+ } else {
+ visitBinary(I, ISD::SUB);
+ }
}
void SelectionDAGLowering::visitBinary(User &I, unsigned Opcode, bool isShift) {