diff options
| author | Chris Lattner <sabre@nondot.org> | 2006-10-13 22:46:18 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-10-13 22:46:18 +0000 |
| commit | dc78cbf45794739ee0fbc8e0c0597f97b5e94df6 (patch) | |
| tree | cc6d6bad36c05893708c23e447c17fb912642370 /lib/CodeGen/SelectionDAG/SelectionDAG.cpp | |
| parent | c50e2bcdf7bff1f9681ab80e52691f274950fab5 (diff) | |
Fix a bug where we incorrectly turned '(X & 0) == 0' into '(X & 0) >> -1',
which is undefined. "0" isn't a power of 2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30947 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/SelectionDAG.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 9c55919e97..00293814b0 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -910,7 +910,7 @@ SDOperand SelectionDAG::SimplifySetCC(MVT::ValueType VT, SDOperand N1, dyn_cast<ConstantSDNode>(N1.getOperand(1))) { if (Cond == ISD::SETNE && C2 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 // Perform the xform if the AND RHS is a single bit. - if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) { + if (isPowerOf2_64(AndRHS->getValue())) { return getNode(ISD::SRL, VT, N1, getConstant(Log2_64(AndRHS->getValue()), TLI.getShiftAmountTy())); @@ -918,7 +918,7 @@ SDOperand SelectionDAG::SimplifySetCC(MVT::ValueType VT, SDOperand N1, } else if (Cond == ISD::SETEQ && C2 == AndRHS->getValue()) { // (X & 8) == 8 --> (X & 8) >> 3 // Perform the xform if C2 is a single bit. - if ((C2 & (C2-1)) == 0) { + if (isPowerOf2_64(C2)) { return getNode(ISD::SRL, VT, N1, getConstant(Log2_64(C2),TLI.getShiftAmountTy())); } |