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| author | Jeff Cohen <jeffc@jolt-lang.org> | 2005-08-19 04:39:48 +0000 |
|---|---|---|
| committer | Jeff Cohen <jeffc@jolt-lang.org> | 2005-08-19 04:39:48 +0000 |
| commit | a92b7c36e97c22bf528706bfceb568ff512de751 (patch) | |
| tree | bf10073cccd22320267c217a79ca2dc7c8c11441 /lib/CodeGen/SelectionDAG/SelectionDAG.cpp | |
| parent | 27d53ba6dd58543b1a3f5f92be522e0d6d75daf8 (diff) | |
Fix VC++ precedence warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22902 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/SelectionDAG.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 7f0725efaa..8fb6070e94 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -1171,7 +1171,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, if (Opcode == ISD::SRA) { // If the sign bit is known to be zero, switch this to a SRL. if (MaskedValueIsZero(N1, - 1ULL << MVT::getSizeInBits(N1.getValueType())-1, + 1ULL << (MVT::getSizeInBits(N1.getValueType())-1), TLI)) return getNode(ISD::SRL, N1.getValueType(), N1, N2); } else { |