Add a couple missing transforms in getSetCC that were triggering assertions

in the PPC Pattern ISel


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21297 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 8 insertions, 1 deletions

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 1926c2adb5..6790adb9d2 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -436,11 +436,18 @@ SDOperand SelectionDAG::getSetCC(ISD::CondCode Cond, MVT::ValueType VT,
         N2C = cast<ConstantSDNode>(N2.Val);
       }
       
+      if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C2 == MinVal)
+        return getConstant(0, VT);      // X < MIN --> false
+        
+      // Canonicalize setgt X, Min --> setne X, Min
+      if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C2 == MinVal)
+        return getSetCC(ISD::SETNE, VT, N1, N2);
+        
       // If we have setult X, 1, turn it into seteq X, 0
       if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C2 == MinVal+1)
         return getSetCC(ISD::SETEQ, VT, N1,
                         getConstant(MinVal, N1.getValueType()));
-      // If we have setult X, 1, turn it into seteq X, 0
+      // If we have setugt X, Max-1, turn it into seteq X, Max
       else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C2 == MaxVal-1)
         return getSetCC(ISD::SETEQ, VT, N1,
                         getConstant(MaxVal, N1.getValueType()));