Allow physregs to occur in the dag with multiple types. Though I don't likethis, it is a requirement on PPC, which can have an f32 value in r3 at onepoint in a function and a f64 value in r3 at another point. :(

This fixes compilation of mesa


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23161 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 8 insertions, 12 deletions

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 2c1aa7522a..9158f78071 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -307,7 +307,8 @@ void SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) {
     ValueTypeNodes[cast<VTSDNode>(N)->getVT()] = 0;
     break;
   case ISD::Register:
-    RegNodes[cast<RegisterSDNode>(N)->getReg()] = 0;
+    RegNodes.erase(std::make_pair(cast<RegisterSDNode>(N)->getReg(),
+                                  N->getValueType(0)));
     break;
   case ISD::SRCVALUE: {
     SrcValueSDNode *SVN = cast<SrcValueSDNode>(N);
@@ -533,18 +534,13 @@ SDOperand SelectionDAG::getCondCode(ISD::CondCode Cond) {
   return SDOperand(CondCodeNodes[Cond], 0);
 }
 
-SDOperand SelectionDAG::getRegister(unsigned Reg, MVT::ValueType VT) {
-  if (Reg >= RegNodes.size())
-    RegNodes.resize(Reg+1);
-  RegisterSDNode *&Result = RegNodes[Reg];
-  if (Result) {
-    assert(Result->getValueType(0) == VT &&
-           "Inconsistent value types for machine registers");
-  } else {
-    Result = new RegisterSDNode(Reg, VT);
-    AllNodes.push_back(Result);
+SDOperand SelectionDAG::getRegister(unsigned RegNo, MVT::ValueType VT) {
+  RegisterSDNode *&Reg = RegNodes[std::make_pair(RegNo, VT)];
+  if (!Reg) {
+    Reg = new RegisterSDNode(RegNo, VT);
+    AllNodes.push_back(Reg);
   }
-  return SDOperand(Result, 0);
+  return SDOperand(Reg, 0);
 }
 
 SDOperand SelectionDAG::SimplifySetCC(MVT::ValueType VT, SDOperand N1,