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authorEvan Cheng <evan.cheng@apple.com>2010-05-20 23:26:43 +0000
committerEvan Cheng <evan.cheng@apple.com>2010-05-20 23:26:43 +0000
commit1cc3984148be113c6e5e470f23c9ddbd37679c5f (patch)
tree29e4aa36a65bfff658e868fdf3191f964de22730 /lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
parent0fe46d9b480ab4851e1fc8bc589d1ed9c8b2a70e (diff)
Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104293 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp')
-rw-r--r--lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp6
1 files changed, 4 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 98dd34fe16..0728cef437 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -1256,8 +1256,10 @@ bool src_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
}
bool hybrid_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const{
- bool LStall = SPQ->getCurCycle() < left->getHeight();
- bool RStall = SPQ->getCurCycle() < right->getHeight();
+ bool LStall = left->SchedulingPref == Sched::Latency &&
+ SPQ->getCurCycle() < left->getHeight();
+ bool RStall = right->SchedulingPref == Sched::Latency &&
+ SPQ->getCurCycle() < right->getHeight();
// If scheduling one of the node will cause a pipeline stall, delay it.
// If scheduling either one of the node will cause a pipeline stall, sort them
// according to their height.