Fix some trailing issues from my introduction of MVT::untyped and its use for REGISTER_SEQUENCE.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133567 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 11 insertions, 1 deletions

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 64faeb4c27..a827187e35 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -290,7 +290,17 @@ static void GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos,
   // Special handling for untyped values.  These values can only come from
   // the expansion of custom DAG-to-DAG patterns.
   if (VT == MVT::untyped) {
-    unsigned Opcode = RegDefPos.GetNode()->getMachineOpcode();
+    const SDNode *Node = RegDefPos.GetNode();
+    unsigned Opcode = Node->getMachineOpcode();
+
+    if (Opcode == TargetOpcode::REG_SEQUENCE) {
+      unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
+      const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
+      RegClass = RC->getID();
+      Cost = 1;
+      return;
+    }
+
     unsigned Idx = RegDefPos.GetIdx();
     const TargetInstrDesc Desc = TII->get(Opcode);
     const TargetRegisterClass *RC = Desc.getRegClass(Idx, TRI);