Add a bit to mark operands of asm's that conflict

with an earlyclobber operand elsewhere.  Propagate
this bit and the earlyclobber bit through SDISel.
Change linear-scan RA not to allocate regs in a way 
that conflicts with an earlyclobber.  See also comments.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56290 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 18 insertions, 5 deletions

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp
index 4ea29063ab..d929aaff7b 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGEmit.cpp
@@ -231,7 +231,8 @@ unsigned ScheduleDAG::getVR(SDValue Op,
 void ScheduleDAG::AddOperand(MachineInstr *MI, SDValue Op,
                              unsigned IIOpNum,
                              const TargetInstrDesc *II,
-                             DenseMap<SDValue, unsigned> &VRBaseMap) {
+                             DenseMap<SDValue, unsigned> &VRBaseMap,
+                             bool overlapsEarlyClobber) {
   if (Op.isMachineOpcode()) {
     // Note that this case is redundant with the final else block, but we
     // include it because it is the most common and it makes the logic
@@ -244,7 +245,9 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDValue Op,
     const TargetInstrDesc &TID = MI->getDesc();
     bool isOptDef = IIOpNum < TID.getNumOperands() &&
       TID.OpInfo[IIOpNum].isOptionalDef();
-    MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
+    MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef, false, false,
+                                             false, 0, false,
+                                             overlapsEarlyClobber));
     
     // Verify that it is right.
     assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
@@ -278,7 +281,9 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDValue Op,
     const ConstantFP *CFP = F->getConstantFPValue();
     MI->addOperand(MachineOperand::CreateFPImm(CFP));
   } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
-    MI->addOperand(MachineOperand::CreateReg(R->getReg(), false));
+    MI->addOperand(MachineOperand::CreateReg(R->getReg(), false, false,
+                                             false, false, 0, false,
+                                             overlapsEarlyClobber));
   } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
     MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(),TGA->getOffset()));
   } else if (BasicBlockSDNode *BB = dyn_cast<BasicBlockSDNode>(Op)) {
@@ -314,7 +319,9 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDValue Op,
            Op.getValueType() != MVT::Flag &&
            "Chain and flag operands should occur at end of operand list!");
     unsigned VReg = getVR(Op, VRBaseMap);
-    MI->addOperand(MachineOperand::CreateReg(VReg, false));
+    MI->addOperand(MachineOperand::CreateReg(VReg, false, false,
+                                             false, false, 0, false,
+                                             overlapsEarlyClobber));
     
     // Verify that it is right.  Note that the reg class of the physreg and the
     // vreg don't necessarily need to match, but the target copy insertion has
@@ -596,6 +603,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, bool IsClone,
       
     // Add all of the operand registers to the instruction.
     for (unsigned i = 2; i != NumOps;) {
+      bool overlapsEarlyClobber = false;
       unsigned Flags =
         cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
       unsigned NumVals = Flags >> 3;
@@ -618,13 +626,18 @@ void ScheduleDAG::EmitNode(SDNode *Node, bool IsClone,
                                                    false, 0, true));
         }
         break;
+      case 7:  // Addressing mode overlapping earlyclobber.
+      case 5:  // Use of register overlapping earlyclobber.
+        overlapsEarlyClobber = true;
+        // fall through
       case 1:  // Use of register.
       case 3:  // Immediate.
       case 4:  // Addressing mode.
         // The addressing mode has been selected, just add all of the
         // operands to the machine instruction.
         for (; NumVals; --NumVals, ++i)
-          AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap);
+          AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap, 
+                     overlapsEarlyClobber);
         break;
       }
     }