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| author | Scott Michel <scottm@aero.org> | 2009-01-26 03:31:40 +0000 |
|---|---|---|
| committer | Scott Michel <scottm@aero.org> | 2009-01-26 03:31:40 +0000 |
| commit | c9c8b2a804b2cd3d33a6a965e06a21ff93968f97 (patch) | |
| tree | 6141f9f0ec12fefbdd984667613aaf33da6068af /lib/CodeGen/SelectionDAG/LegalizeTypes.cpp | |
| parent | 5bf4b7556f025587a8d1a14bd0fb39c12fc9c170 (diff) | |
CellSPU:
- Rename fcmp.ll test to fcmp32.ll, start adding new double tests to fcmp64.ll
- Fix select_bits.ll test
- Capitulate to the DAGCombiner and move i64 constant loads to instruction
selection (SPUISelDAGtoDAG.cpp).
<rant>DAGCombiner will insert all kinds of 64-bit optimizations after
operation legalization occurs and now we have to do most of the work that
instruction selection should be doing twice (once to determine if v2i64
build_vector can be handled by SelectCode(), which then runs all of the
predicates a second time to select the necessary instructions.) But,
CellSPU is a good citizen.</rant>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62990 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/LegalizeTypes.cpp')
0 files changed, 0 insertions, 0 deletions