diff options
| author | Chris Lattner <sabre@nondot.org> | 2005-01-12 18:19:52 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-01-12 18:19:52 +0000 |
| commit | 2dad454af674cb41a14a85ad6ce5c85c43959acd (patch) | |
| tree | a6605e303533ef15a26d0f4872230fa620c0c6a7 /lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | |
| parent | 9ffdfb6bae9a8befd23e002f71f08aa42caee627 (diff) | |
Fix sign extend to long. When coming from sbyte, we used to generate:
movsbl 4(%esp), %eax
movl %eax, %edx
sarl $7, %edx
Now we generate:
movsbl 4(%esp), %eax
movl %eax, %edx
sarl $31, %edx
Which is right.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19515 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/LegalizeDAG.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index f3b344bb8c..64c686efc6 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -805,8 +805,8 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){ // The high part is obtained by SRA'ing all but one of the bits of the lo // part. - unsigned SrcSize = MVT::getSizeInBits(Node->getOperand(0).getValueType()); - Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(SrcSize-1, MVT::i8)); + unsigned LoSize = MVT::getSizeInBits(Lo.getValueType()); + Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1, MVT::i8)); break; } case ISD::ZERO_EXTEND: |