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| author | Dan Gohman <gohman@apple.com> | 2010-07-01 02:58:57 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2010-07-01 02:58:57 +0000 |
| commit | 20d4be151b54feb18aa1e5cc04033a4aa64137ae (patch) | |
| tree | 5df800c11b786098efd82b64d5f21b8c3d200f35 /lib/CodeGen/SelectionDAG/FastISel.cpp | |
| parent | abd1d859b3c35957a3dd5965cf1fd420df0d20e3 (diff) | |
Enable on-demand fast-isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107377 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/FastISel.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/FastISel.cpp | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp index cc8c3c70ac..2d6b78840f 100644 --- a/lib/CodeGen/SelectionDAG/FastISel.cpp +++ b/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -161,7 +161,10 @@ unsigned FastISel::materializeRegForValue(const Value *V, MVT VT) { } } } else if (const Operator *Op = dyn_cast<Operator>(V)) { - if (!SelectOperator(Op, Op->getOpcode())) return 0; + if (!SelectOperator(Op, Op->getOpcode())) + if (!isa<Instruction>(Op) || + !TargetSelectInstruction(cast<Instruction>(Op))) + return 0; Reg = lookUpRegForValue(Op); } else if (isa<UndefValue>(V)) { Reg = createResultReg(TLI.getRegClassFor(VT)); |