Clean up my own mess.

X86 lowering normalize vector 0 to v4i32. However DAGCombine can fold (sub x, x) -> 0 after legalization. It can create a zero vector of a type that's not expected (e.g. v8i16). We don't want to disable the optimization since leaving a (sub x, x) is really bad. Add isel patterns for other types of vector 0 to ensure correctness. It's highly unlikely to happen other than in bugpoint reduced test cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48279 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 1 insertions, 7 deletions

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 5a6077a3ca..0e719f844e 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -1102,14 +1102,8 @@ SDOperand DAGCombiner::visitSUB(SDNode *N) {
   }
   
   // fold (sub x, x) -> 0
-  if (N0 == N1) {
-    if (AfterLegalize && ISD::isBuildVectorAllZeros(N0.Val))
-      // For example, zero vectors might be normalized to a particular vector
-      // type to ensure they are CSE'd. Avoid issuing zero vector nodes of
-      // *unexpected* type after legalization.
-      return N0;
+  if (N0 == N1)
     return DAG.getConstant(0, N->getValueType(0));
-  }
   // fold (sub c1, c2) -> c1-c2
   if (N0C && N1C)
     return DAG.getNode(ISD::SUB, VT, N0, N1);