Add checks to make sure we don't create bogus extend nodes, and fix a bug

where we were doing exactly that which was causing failures on x86 and
alpha.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26284 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 10 insertions, 4 deletions

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 4f7df4f436..bdb32ed78f 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -665,6 +665,9 @@ SDOperand DAGCombiner::visitADD(SDNode *N) {
   // fold (A+(B-A)) -> B
   if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
     return N1.getOperand(0);
+  // 
+  if (SimplifyDemandedBits(SDOperand(N, 0)))
+    return SDOperand();
   return SDOperand();
 }
 
@@ -2297,13 +2300,16 @@ SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
     // Get a SetCC of the condition
     // FIXME: Should probably make sure that setcc is legal if we ever have a
     // target where it isn't.
-    SDOperand Temp, SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
-    WorkList.push_back(SCC.Val);
+    SDOperand Temp, SCC;
     // cast from setcc result type to select result type
-    if (AfterLegalize)
+    if (AfterLegalize) {
+      SCC  = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
       Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
-    else
+    } else {
+      SCC  = DAG.getSetCC(MVT::i1, N0, N1, CC);
       Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
+    }
+    WorkList.push_back(SCC.Val);
     WorkList.push_back(Temp.Val);
     // shl setcc result by log2 n2c
     return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,