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authorNate Begeman <natebegeman@mac.com>2006-01-28 01:06:30 +0000
committerNate Begeman <natebegeman@mac.com>2006-01-28 01:06:30 +0000
commit61af66e687561a821181f742677c38a933a6fea0 (patch)
treeb69180cac8ad7f938eda06282a14c9ddc35ee571 /lib/CodeGen/SelectionDAG/DAGCombiner.cpp
parent0ff5c27a00926e2ea4c99b3d5e62c55b29faf06b (diff)
Add a missing case to the dag combiner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25723 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/DAGCombiner.cpp')
-rw-r--r--lib/CodeGen/SelectionDAG/DAGCombiner.cpp5
1 files changed, 3 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 99c272e001..a96c59b340 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -1035,9 +1035,10 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
WorkList.push_back(ANDNode.Val);
return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode);
}
- // fold (and (shl/srl x), (shl/srl y)) -> (shl/srl (and x, y))
+ // fold (and (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (and x, y))
if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
- (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL)) &&
+ (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) ||
+ (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) &&
N0.getOperand(1) == N1.getOperand(1)) {
SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
N0.getOperand(0), N1.getOperand(0));