diff options
| author | Chris Lattner <sabre@nondot.org> | 2006-04-28 23:33:20 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-04-28 23:33:20 +0000 |
| commit | 25c344a7589054bd3f6ad31c777a02fb4916c31f (patch) | |
| tree | 27e81c094a165c0a7bf5e2b59f3ddf0c5456c929 /lib/CodeGen/SelectionDAG/DAGCombiner.cpp | |
| parent | 55c25f2a2fcf8c345f2b126cec0aa706a1892f2b (diff) | |
Remove a bogus transformation. This fixes SingleSource/UnitTests/2006-01-23-InitializedBitField.c
with some changes I have to the new CFE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28022 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/DAGCombiner.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index e9b30cb38b..ac70150f8e 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -1899,13 +1899,6 @@ SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) return DAG.getZeroExtendInReg(N0, EVT); - // fold (sext_in_reg (srl x)) -> sra x - if (N0.getOpcode() == ISD::SRL && - N0.getOperand(1).getOpcode() == ISD::Constant && - cast<ConstantSDNode>(N0.getOperand(1))->getValue() == EVTBits) { - return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0), - N0.getOperand(1)); - } // fold (sext_inreg (extload x)) -> (sextload x) if (N0.getOpcode() == ISD::EXTLOAD && EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && |