diff options
| author | Jim Grosbach <grosbach@apple.com> | 2009-10-19 22:27:30 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2009-10-19 22:27:30 +0000 |
| commit | d482f55af135081aee7f7ab972bb8973f189c88f (patch) | |
| tree | ab7c243668857e2eeed65a76d0a565783c224de8 /lib/CodeGen/RegisterScavenging.cpp | |
| parent | 4d1522234192704f45dfd2527c2913fa60be616e (diff) | |
Adjust the scavenge register spilling to allow the target to choose an
appropriate restore location for the spill as well as perform the actual
save and restore.
The Thumb1 target uses this to make sure R12 is not clobbered while a spilled
scavenger register is live there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84554 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegisterScavenging.cpp')
| -rw-r--r-- | lib/CodeGen/RegisterScavenging.cpp | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/lib/CodeGen/RegisterScavenging.cpp b/lib/CodeGen/RegisterScavenging.cpp index 5f1c4e2594..5fa28d281a 100644 --- a/lib/CodeGen/RegisterScavenging.cpp +++ b/lib/CodeGen/RegisterScavenging.cpp @@ -300,7 +300,7 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC, // If the target knows how to save/restore the register, let it do so; // otherwise, use the emergency stack spill slot. - if (!TRI->saveScavengerRegister(*MBB, I, RC, SReg)) { + if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg)) { // Spill the scavenged register before I. assert(ScavengingFrameIndex >= 0 && "Cannot scavenge register without an emergency spill slot!"); @@ -310,8 +310,7 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC, // Restore the scavenged register before its use (or first terminator). TII->loadRegFromStackSlot(*MBB, UseMI, SReg, ScavengingFrameIndex, RC); - } else - TRI->restoreScavengerRegister(*MBB, UseMI, RC, SReg); + } ScavengeRestore = prior(UseMI); |