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authorAlkis Evlogimenos <alkis@evlogimenos.com>2004-02-13 21:01:20 +0000
committerAlkis Evlogimenos <alkis@evlogimenos.com>2004-02-13 21:01:20 +0000
commitbe766c72464116a445a02b542a450c4274bab5d0 (patch)
treedf819681fc4d2a770e0aecceca8d5473a7d66574 /lib/CodeGen/RegAllocSimple.cpp
parent903b22cd51d82ba1c1c5ee5d37b7eb7911c755ee (diff)
Remove getAllocatedRegNum(). Use getReg() instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11393 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegAllocSimple.cpp')
-rw-r--r--lib/CodeGen/RegAllocSimple.cpp8
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index a40ec64077..e313004ff4 100644
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -173,7 +173,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
MachineOperand &op = MI->getOperand(i);
if (op.isRegister() && MRegisterInfo::isVirtualRegister(op.getReg())) {
- unsigned virtualReg = (unsigned) op.getAllocatedRegNum();
+ unsigned virtualReg = (unsigned) op.getReg();
DEBUG(std::cerr << "op: " << op << "\n");
DEBUG(std::cerr << "\t inst[" << i << "]: ";
MI->print(std::cerr, *TM));
@@ -187,11 +187,11 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
// must be same register number as the first operand
// This maps a = b + c into b += c, and saves b into a's spot
assert(MI->getOperand(1).isRegister() &&
- MI->getOperand(1).getAllocatedRegNum() &&
+ MI->getOperand(1).getReg() &&
MI->getOperand(1).isUse() &&
"Two address instruction invalid!");
- physReg = MI->getOperand(1).getAllocatedRegNum();
+ physReg = MI->getOperand(1).getReg();
} else {
physReg = getFreeReg(virtualReg);
}
@@ -205,7 +205,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
}
MI->SetMachineOperandReg(i, physReg);
DEBUG(std::cerr << "virt: " << virtualReg <<
- ", phys: " << op.getAllocatedRegNum() << "\n");
+ ", phys: " << op.getReg() << "\n");
}
}
RegClassIdx.clear();