diff options
| author | Vikram S. Adve <vadve@cs.uiuc.edu> | 2003-05-27 00:05:23 +0000 |
|---|---|---|
| committer | Vikram S. Adve <vadve@cs.uiuc.edu> | 2003-05-27 00:05:23 +0000 |
| commit | 5f2180c53330502eb2f0f5bf3f21a838ad800906 (patch) | |
| tree | fd2e03a6e2409e48c1d145b16ebb8ff41c77003d /lib/CodeGen/RegAllocLocal.cpp | |
| parent | 49cab03c8149619b5c07e473b08d73b91aefb35c (diff) | |
(1) Added special register class containing (for now) %fsr.
Fixed spilling of %fcc[0-3] which are part of %fsr.
(2) Moved some machine-independent reg-class code to class TargetRegInfo
from SparcReg{Class,}Info.
(3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()
and related functions and flags. Fixed several bugs where only
"isDef" was being checked, not "isDefAndUse".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6341 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegAllocLocal.cpp')
| -rw-r--r-- | lib/CodeGen/RegAllocLocal.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp index 80100445a4..fed05b7dbb 100644 --- a/lib/CodeGen/RegAllocLocal.cpp +++ b/lib/CodeGen/RegAllocLocal.cpp @@ -489,7 +489,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) { // Loop over all of the operands of the instruction, spilling registers that // are defined, and marking explicit destinations in the PhysRegsUsed map. for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) - if ((MI->getOperand(i).opIsDef() || MI->getOperand(i).opIsDefAndUse()) && + if ((MI->getOperand(i).opIsDefOnly() || MI->getOperand(i).opIsDefAndUse()) && MI->getOperand(i).isPhysicalRegister()) { unsigned Reg = MI->getOperand(i).getAllocatedRegNum(); spillPhysReg(MBB, I, Reg); // Spill any existing value in the reg @@ -512,8 +512,8 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) { // we need to scavenge a register. // for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) - if (MI->getOperand(i).opIsDef() && - MI->getOperand(i).isVirtualRegister()) { + if ((MI->getOperand(i).opIsDefOnly() || MI->getOperand(i).opIsDefAndUse()) + && MI->getOperand(i).isVirtualRegister()) { unsigned DestVirtReg = MI->getOperand(i).getAllocatedRegNum(); unsigned DestPhysReg; |