diff options
| author | Owen Anderson <resistor@mac.com> | 2008-07-22 22:46:49 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2008-07-22 22:46:49 +0000 |
| commit | a1566f2e12ce87a5bca30bc0189a0cdbb40136a4 (patch) | |
| tree | fecdd6cd2ded8963a4015584d9de5f7f4329a765 /lib/CodeGen/RegAllocLinearScan.cpp | |
| parent | 38bcec13e89b33fd6b0553ec47667744c54fbb7b (diff) | |
Change the heuristics used in the coalescer, register allocator, and within
live intervals itself to use an instruction count approximation that is
not affected by inserting empty indices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53937 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegAllocLinearScan.cpp')
| -rw-r--r-- | lib/CodeGen/RegAllocLinearScan.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp index a26924be62..4df172d40c 100644 --- a/lib/CodeGen/RegAllocLinearScan.cpp +++ b/lib/CodeGen/RegAllocLinearScan.cpp @@ -851,7 +851,8 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) if (minWeight == HUGE_VALF) { // All registers must have inf weight. Just grab one! minReg = BestPhysReg ? BestPhysReg : *RC->allocation_order_begin(*mf_); - if (cur->weight == HUGE_VALF || cur->getSize() == 1) + if (cur->weight == HUGE_VALF || + li_->getApproximateInstructionCount(*cur) == 1) // Spill a physical register around defs and uses. li_->spillPhysRegAroundRegDefsUses(*cur, minReg, *vrm_); } |