Teach coalescer about earlyclobber bits.

Check bits for preferred register.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56384 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 5 insertions, 2 deletions

diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp
index df9d393a8f..5a1944fd5f 100644
--- a/lib/CodeGen/RegAllocLinearScan.cpp
+++ b/lib/CodeGen/RegAllocLinearScan.cpp
@@ -1122,9 +1122,12 @@ unsigned RALinScan::getFreePhysReg(LiveInterval *cur) {
   unsigned FreeRegInactiveCount = 0;
 
   // If copy coalescer has assigned a "preferred" register, check if it's
-  // available first.
+  // available first.  Coalescer can create new earlyclobber interferences,
+  // so we need to check that.
   if (cur->preference) {
-    if (prt_->isRegAvail(cur->preference) && RC->contains(cur->preference)) {
+    if (prt_->isRegAvail(cur->preference) && 
+        RC->contains(cur->preference) &&
+        noEarlyClobberConflict(cur, cur->preference)) {
       DOUT << "\t\tassigned the preferred register: "
            << tri_->getName(cur->preference) << "\n";
       return cur->preference;