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authorChris Lattner <sabre@nondot.org>2004-07-19 05:02:09 +0000
committerChris Lattner <sabre@nondot.org>2004-07-19 05:02:09 +0000
commit331cb7dde1bf0c52bfd17570d36e56b934d559f5 (patch)
treed45194b2f1b1c139b4a052f2753535f5af577dde /lib/CodeGen/RegAllocLinearScan.cpp
parent59073e02ccd79c8728e439dfe6869091b84d669c (diff)
Fix assertion to not dereference end!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14991 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegAllocLinearScan.cpp')
-rw-r--r--lib/CodeGen/RegAllocLinearScan.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp
index 24508fbbb0..dbed7973fc 100644
--- a/lib/CodeGen/RegAllocLinearScan.cpp
+++ b/lib/CodeGen/RegAllocLinearScan.cpp
@@ -399,8 +399,8 @@ void RA::assignRegOrStackSlotAtInterval(IntervalPtrs::value_type cur)
std::vector<LiveInterval*>::iterator addedItEnd = added.end();
for (IntervalPtrs::iterator i = unhandled_.begin(), e =unhandled_.end();
i != e && addedIt != addedItEnd; ++i) {
- while ((*i)->start() > (*addedIt)->start() &&
- addedIt != addedItEnd) {
+ while (addedIt != addedItEnd &&
+ (*i)->start() > (*addedIt)->start()) {
#ifndef NDEBUG
// This code only works if addIntervalsForSpills retursn a
// sorted interval list. Assert this is the case now.