Copy coalescing change to prevent a physical register from being pin to a

long live interval that has low usage density.
1. Change order of coalescing to join physical registers with virtual
   registers first before virtual register intervals become too long.
2. Check size and usage density to determine if it's worthwhile to join.
3. If joining is aborted, assign virtual register live interval allocation
   preference field to the physical register.
4. Register allocator should try to allocate to the preferred register
   first (if available) to create identify moves that can be eliminated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36218 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 22 insertions, 9 deletions

diff --git a/lib/CodeGen/RegAllocLinearScan.cpp b/lib/CodeGen/RegAllocLinearScan.cpp
index 8ce7e8a73f..0ff989f674 100644
--- a/lib/CodeGen/RegAllocLinearScan.cpp
+++ b/lib/CodeGen/RegAllocLinearScan.cpp
@@ -563,15 +563,17 @@ void RA::assignRegOrStackSlotAtInterval(LiveInterval* cur)
 
   // Find a register to spill.
   float minWeight = HUGE_VALF;
-  unsigned minReg = 0;
-  for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
-       e = RC->allocation_order_end(*mf_); i != e; ++i) {
-    unsigned reg = *i;
-    if (minWeight > SpillWeights[reg]) {
-      minWeight = SpillWeights[reg];
-      minReg = reg;
+  unsigned minReg = cur->preference;  // Try the preferred register first.
+  
+  if (!minReg || SpillWeights[minReg] == HUGE_VALF)
+    for (TargetRegisterClass::iterator i = RC->allocation_order_begin(*mf_),
+           e = RC->allocation_order_end(*mf_); i != e; ++i) {
+      unsigned reg = *i;
+      if (minWeight > SpillWeights[reg]) {
+        minWeight = SpillWeights[reg];
+        minReg = reg;
+      }
     }
-  }
   
   // If we didn't find a register that is spillable, try aliases?
   if (!minReg) {
@@ -778,7 +780,18 @@ unsigned RA::getFreePhysReg(LiveInterval *cur) {
 
   unsigned FreeReg = 0;
   unsigned FreeRegInactiveCount = 0;
-  
+
+  // If copy coalescer has assigned a "preferred" register, check if it's
+  // available first.
+  if (cur->preference)
+    if (prt_->isRegAvail(cur->preference)) {
+      DOUT << "\t\tassigned the preferred register: "
+           << mri_->getName(cur->preference) << "\n";
+      return cur->preference;
+    } else
+      DOUT << "\t\tunable to assign the preferred register: "
+           << mri_->getName(cur->preference) << "\n";
+
   // Scan for the first available register.
   TargetRegisterClass::iterator I = rc->allocation_order_begin(*mf_);
   TargetRegisterClass::iterator E = rc->allocation_order_end(*mf_);