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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-03-07 22:42:16 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-03-07 22:42:16 +0000 |
| commit | 1973b3e2541f95c87e4acb7e134362ff306ec9ed (patch) | |
| tree | 9b4ab014985a01f9cf6df6542caa96697f765819 /lib/CodeGen/RegAllocGreedy.cpp | |
| parent | be2119e8e2bc7006cfd638a24367acbfda625d16 (diff) | |
Make the UselessRegs argument optional in the LiveRangeEdit constructor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127181 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegAllocGreedy.cpp')
| -rw-r--r-- | lib/CodeGen/RegAllocGreedy.cpp | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/lib/CodeGen/RegAllocGreedy.cpp b/lib/CodeGen/RegAllocGreedy.cpp index 642805e08a..917e64049c 100644 --- a/lib/CodeGen/RegAllocGreedy.cpp +++ b/lib/CodeGen/RegAllocGreedy.cpp @@ -601,8 +601,7 @@ void RAGreedy::splitAroundRegion(LiveInterval &VirtReg, unsigned PhysReg, SmallVector<IndexPair, 8> InterferenceRanges; mapGlobalInterference(PhysReg, InterferenceRanges); - SmallVector<LiveInterval*, 4> SpillRegs; - LiveRangeEdit LREdit(VirtReg, NewVRegs, SpillRegs); + LiveRangeEdit LREdit(VirtReg, NewVRegs); SE->reset(LREdit); // Create the main cross-block interval. @@ -1130,8 +1129,7 @@ unsigned RAGreedy::tryLocalSplit(LiveInterval &VirtReg, AllocationOrder &Order, << '-' << Uses[BestAfter] << ", " << BestDiff << ", " << (BestAfter - BestBefore + 1) << " instrs\n"); - SmallVector<LiveInterval*, 4> SpillRegs; - LiveRangeEdit LREdit(VirtReg, NewVRegs, SpillRegs); + LiveRangeEdit LREdit(VirtReg, NewVRegs); SE->reset(LREdit); SE->openIntv(); @@ -1183,8 +1181,7 @@ unsigned RAGreedy::trySplit(LiveInterval &VirtReg, AllocationOrder &Order, if (Stage < RS_Block) { SplitAnalysis::BlockPtrSet Blocks; if (SA->getMultiUseBlocks(Blocks)) { - SmallVector<LiveInterval*, 4> SpillRegs; - LiveRangeEdit LREdit(VirtReg, NewVRegs, SpillRegs); + LiveRangeEdit LREdit(VirtReg, NewVRegs); SE->reset(LREdit); SE->splitSingleBlocks(Blocks); setStage(NewVRegs.begin(), NewVRegs.end(), RS_Block); |