diff options
| author | Andrew Trick <atrick@apple.com> | 2010-12-09 18:15:21 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2010-12-09 18:15:21 +0000 |
| commit | b853e6c3702149cdbbd6fa404334e3ba0055641a (patch) | |
| tree | 2daa08a7cd8703e8d397588a903545c4dfb965d9 /lib/CodeGen/RegAllocBasic.cpp | |
| parent | f2f516fc2680168caac9981a4dd17cc37c639c71 (diff) | |
Added register reassignment prototype to RAGreedy. It's a simple
heuristic to reshuffle register assignments when we can't find an
available reg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121388 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/RegAllocBasic.cpp')
| -rw-r--r-- | lib/CodeGen/RegAllocBasic.cpp | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/lib/CodeGen/RegAllocBasic.cpp b/lib/CodeGen/RegAllocBasic.cpp index 88446aa505..753688b200 100644 --- a/lib/CodeGen/RegAllocBasic.cpp +++ b/lib/CodeGen/RegAllocBasic.cpp @@ -435,15 +435,13 @@ unsigned RABasic::selectOrSplit(LiveInterval &VirtReg, LiveInterval *interferingVirtReg = Queries[interfReg].firstInterference().liveUnionPos().value(); - // The current VirtReg must either spillable, or one of its interferences + // The current VirtReg must either be spillable, or one of its interferences // must have less spill weight. if (interferingVirtReg->weight < VirtReg.weight ) { PhysRegSpillCands.push_back(PhysReg); } } // Try to spill another interfering reg with less spill weight. - // - // FIXME: RAGreedy will sort this list by spill weight. for (SmallVectorImpl<unsigned>::iterator PhysRegI = PhysRegSpillCands.begin(), PhysRegE = PhysRegSpillCands.end(); PhysRegI != PhysRegE; ++PhysRegI) { |