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| author | Evan Cheng <evan.cheng@apple.com> | 2009-10-01 08:21:18 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2009-10-01 08:21:18 +0000 |
| commit | 799d697bf8d45ec404d0d105fc788ea5cf81c841 (patch) | |
| tree | 8af1dac2ce2c4fcca7840ed2bf730f7c2f8ca64b /lib/CodeGen/PostRASchedulerList.cpp | |
| parent | 8f3ec31133494d104f46b09d52377e6c4739749d (diff) | |
Add instruction flags: hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq. When
set, these flags indicate the instructions source / def operands have special
register allocation requirement that are not captured in their register classes.
Post-allocation passes (e.g. post-alloc scheduler) should not change their
allocations. e.g. ARM::LDRD require the two definitions to be allocated
even / odd register pair.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83196 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/PostRASchedulerList.cpp')
0 files changed, 0 insertions, 0 deletions