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| author | Andrew Trick <atrick@apple.com> | 2012-01-14 02:17:12 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-01-14 02:17:12 +0000 |
| commit | 5e920d7c83c20474fc3470209869978628ccf8da (patch) | |
| tree | 338319ef98616a63d15a3b93c2109dd20190dd7c /lib/CodeGen/PostRASchedulerList.cpp | |
| parent | e9ef4ed13ba84ef27da831afa27b7955c8f09530 (diff) | |
misched: Added ScheduleDAGInstrs::IsPostRA
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148172 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/PostRASchedulerList.cpp')
| -rw-r--r-- | lib/CodeGen/PostRASchedulerList.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp index fa832c867a..1e06ee9199 100644 --- a/lib/CodeGen/PostRASchedulerList.cpp +++ b/lib/CodeGen/PostRASchedulerList.cpp @@ -185,7 +185,7 @@ SchedulePostRATDList::SchedulePostRATDList( AliasAnalysis *AA, const RegisterClassInfo &RCI, TargetSubtargetInfo::AntiDepBreakMode AntiDepMode, SmallVectorImpl<TargetRegisterClass*> &CriticalPathRCs) - : ScheduleDAGInstrs(MF, MLI, MDT), Topo(SUnits), AA(AA), + : ScheduleDAGInstrs(MF, MLI, MDT, /*IsPostRA=*/true), Topo(SUnits), AA(AA), KillIndices(TRI->getNumRegs()) { const TargetMachine &TM = MF.getTarget(); |