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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2009-12-22 21:48:20 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2009-12-22 21:48:20 +0000 |
| commit | 5711564b091c39188775aee2768ad36a9b9a99b2 (patch) | |
| tree | 337d113f4dac5f2559250c695bba4c93a80ba6d6 /lib/CodeGen/MachineVerifier.cpp | |
| parent | 3ea58b6d7a6357018f4f78396b457f86198a7afa (diff) | |
Allow explicit %reg0 operands beyond what the .td file describes.
ARM uses these to indicate predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91922 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/MachineVerifier.cpp')
| -rw-r--r-- | lib/CodeGen/MachineVerifier.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/CodeGen/MachineVerifier.cpp b/lib/CodeGen/MachineVerifier.cpp index 917d0535b2..959269f85f 100644 --- a/lib/CodeGen/MachineVerifier.cpp +++ b/lib/CodeGen/MachineVerifier.cpp @@ -553,7 +553,8 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) { report("Explicit operand marked as implicit", MO, MONum); } } else { - if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic()) + // ARM adds %reg0 operands to indicate predicates. We'll allow that. + if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic() && MO->getReg()) report("Extra explicit operand on non-variadic instruction", MO, MONum); } |