diff options
| author | Alkis Evlogimenos <alkis@evlogimenos.com> | 2004-02-13 21:01:20 +0000 |
|---|---|---|
| committer | Alkis Evlogimenos <alkis@evlogimenos.com> | 2004-02-13 21:01:20 +0000 |
| commit | be766c72464116a445a02b542a450c4274bab5d0 (patch) | |
| tree | df819681fc4d2a770e0aecceca8d5473a7d66574 /lib/CodeGen/MachineInstr.cpp | |
| parent | 903b22cd51d82ba1c1c5ee5d37b7eb7911c755ee (diff) | |
Remove getAllocatedRegNum(). Use getReg() instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11393 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/MachineInstr.cpp')
| -rw-r--r-- | lib/CodeGen/MachineInstr.cpp | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp index b5ffd6215a..ca2c2db4a8 100644 --- a/lib/CodeGen/MachineInstr.cpp +++ b/lib/CodeGen/MachineInstr.cpp @@ -187,7 +187,7 @@ static inline std::ostream& OutputValue(std::ostream &os, const Value* val) { static inline void OutputReg(std::ostream &os, unsigned RegNo, const MRegisterInfo *MRI = 0) { if (MRI) { - if (RegNo < MRegisterInfo::FirstVirtualRegister) + if (MRegisterInfo::isPhysicalRegister(RegNo)) os << "%" << MRI->get(RegNo).Name; else os << "%reg" << RegNo; @@ -219,14 +219,14 @@ static void print(const MachineOperand &MO, std::ostream &OS, OS << "=="; } if (MO.hasAllocatedReg()) - OutputReg(OS, MO.getAllocatedRegNum(), MRI); + OutputReg(OS, MO.getReg(), MRI); break; case MachineOperand::MO_CCRegister: OS << "%ccreg"; OutputValue(OS, MO.getVRegValue()); if (MO.hasAllocatedReg()) { OS << "=="; - OutputReg(OS, MO.getAllocatedRegNum(), MRI); + OutputReg(OS, MO.getReg(), MRI); } break; case MachineOperand::MO_MachineRegister: @@ -360,7 +360,7 @@ std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) { { case MachineOperand::MO_VirtualRegister: if (MO.hasAllocatedReg()) - OutputReg(OS, MO.getAllocatedRegNum()); + OutputReg(OS, MO.getReg()); if (MO.getVRegValue()) { if (MO.hasAllocatedReg()) OS << "=="; @@ -373,7 +373,7 @@ std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) { OutputValue(OS, MO.getVRegValue()); if (MO.hasAllocatedReg()) { OS << "=="; - OutputReg(OS, MO.getAllocatedRegNum()); + OutputReg(OS, MO.getReg()); } break; case MachineOperand::MO_MachineRegister: |