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| author | Chris Lattner <sabre@nondot.org> | 2007-12-30 20:55:08 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2007-12-30 20:55:08 +0000 |
| commit | 0974d9a5247a1f70ab739191ce5d768488a0f8aa (patch) | |
| tree | b2be3cd7e66a6d144d5656d8a14704722207d1b8 /lib/CodeGen/MachineInstr.cpp | |
| parent | 9e3304900ff69c4920fea7369c9c36916c4a6a6a (diff) | |
two register machineoperands are not identical unless their subregs match.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45455 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/MachineInstr.cpp')
| -rw-r--r-- | lib/CodeGen/MachineInstr.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp index f54cbe7f1c..e8f692e15f 100644 --- a/lib/CodeGen/MachineInstr.cpp +++ b/lib/CodeGen/MachineInstr.cpp @@ -153,7 +153,8 @@ bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const { switch (getType()) { default: assert(0 && "Unrecognized operand type"); case MachineOperand::MO_Register: - return getReg() == Other.getReg() && isDef() == Other.isDef(); + return getReg() == Other.getReg() && isDef() == Other.isDef() && + getSubReg() == Other.getSubReg(); case MachineOperand::MO_Immediate: return getImm() == Other.getImm(); case MachineOperand::MO_MachineBasicBlock: |