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| author | Misha Brukman <brukman+llvm@gmail.com> | 2004-10-23 06:05:49 +0000 |
|---|---|---|
| committer | Misha Brukman <brukman+llvm@gmail.com> | 2004-10-23 06:05:49 +0000 |
| commit | da8d96d1a1769d0614c46d9880ac3c21cbc8e74c (patch) | |
| tree | 9d4309fc6fb9c43889c290fa99f29424fe346990 /lib/CodeGen/MachineBasicBlock.cpp | |
| parent | 15f74b3f4f371d5ef556644a7a2d61a0993a8053 (diff) | |
Fix the SPR field for MTLR, MFLR, MTCTR, and MFCTR instructions.
The decimal value given in the manual (8 or 9) really needs to be multiplied by
a factor of 32 because of the group of 5 zero bits after the register code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17182 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/MachineBasicBlock.cpp')
0 files changed, 0 insertions, 0 deletions