diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2007-09-26 06:25:56 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2007-09-26 06:25:56 +0000 |
| commit | 9efce638d307b2c71bd7f0258d47501661434c27 (patch) | |
| tree | ff8e23600c1a2e9ba48a6010a2ec8a84c84f785b /lib/CodeGen/LowerSubregs.cpp | |
| parent | 61001b8bd47adcf413dbb5b2a8c95cf22ec4bf7a (diff) | |
Allow copyRegToReg to emit cross register classes copies.
Tested with "make check"!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42346 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/LowerSubregs.cpp')
| -rw-r--r-- | lib/CodeGen/LowerSubregs.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/CodeGen/LowerSubregs.cpp b/lib/CodeGen/LowerSubregs.cpp index 7acd03e1cc..ba2a193ca4 100644 --- a/lib/CodeGen/LowerSubregs.cpp +++ b/lib/CodeGen/LowerSubregs.cpp @@ -88,7 +88,7 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) { assert(TRC == getPhysicalRegisterRegClass(MRI, SrcReg) && "Extract subreg and Dst must be of same register class"); - MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC); + MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC); MachineBasicBlock::iterator dMI = MI; DOUT << "subreg: " << *(--dMI); } @@ -157,7 +157,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { } else { TRC1 = MF.getSSARegMap()->getRegClass(InsReg); } - MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1); + MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1); #ifndef NDEBUG MachineBasicBlock::iterator dMI = MI; @@ -184,7 +184,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { assert(TRC0 == getPhysicalRegisterRegClass(MRI, SrcReg) && "Insert superreg and Dst must be of same register class"); - MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0); + MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0, TRC0); #ifndef NDEBUG MachineBasicBlock::iterator dMI = MI; @@ -206,7 +206,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { } else { TRC1 = MF.getSSARegMap()->getRegClass(InsReg); } - MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1); + MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1); #ifndef NDEBUG MachineBasicBlock::iterator dMI = MI; |