Use MCPhysReg for RegisterClassInfo allocation orders.

This saves a bit of memory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168852 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 3 insertions, 3 deletions

diff --git a/lib/CodeGen/AllocationOrder.cpp b/lib/CodeGen/AllocationOrder.cpp
index 96c907aa9c..bad4912e72 100644
--- a/lib/CodeGen/AllocationOrder.cpp
+++ b/lib/CodeGen/AllocationOrder.cpp
@@ -42,7 +42,7 @@ AllocationOrder::AllocationOrder(unsigned VirtReg,
   if (HintPair.first) {
     const TargetRegisterInfo &TRI = VRM.getTargetRegInfo();
     // The remaining allocation order may depend on the hint.
-    ArrayRef<uint16_t> Order =
+    ArrayRef<MCPhysReg> Order =
       TRI.getRawAllocationOrder(RC, HintPair.first, Hint,
                                 VRM.getMachineFunction());
     if (Order.empty())
@@ -50,7 +50,7 @@ AllocationOrder::AllocationOrder(unsigned VirtReg,
 
     // Copy the allocation order with reserved registers removed.
     OwnedBegin = true;
-    unsigned *P = new unsigned[Order.size()];
+    MCPhysReg *P = new MCPhysReg[Order.size()];
     Begin = P;
     for (unsigned i = 0; i != Order.size(); ++i)
       if (!MRI.isReserved(Order[i]))
@@ -63,7 +63,7 @@ AllocationOrder::AllocationOrder(unsigned VirtReg,
   } else {
     // If there is no hint or just a normal hint, use the cached allocation
     // order from RegisterClassInfo.
-    ArrayRef<unsigned> O = RCI.getOrder(RC);
+    ArrayRef<MCPhysReg> O = RCI.getOrder(RC);
     Begin = O.begin();
     End = O.end();
   }